Friday, January 27, 2012

FPGA to 74HC595 Shift Register Module in Verilog

I have had this 74HC595 IC sitting around for quite some time. And earlier this week I decided it was time for me to actually start using it...or at least start learning how I could use it. This chip is a Serial-In Parallel-Out 8-bit shift register that can be used in a variety of ways and it can be cascaded with more of these ICs to create a larger shift register if needed. My plan is to use this newly developed module to act as a low pin count interface between the FPGA and my 16x2 Character LCD module. This will allow me to utilize 4-wires to control the 8-bit parallel interface on the LCD (not including the LCD control lines). This reduced the FPGA pin utilization from 11 pins down to 7 pins...not to shabby. Anyways for those that are interested, the code is linked below. Please note: this module is very much application specific and that it does not enable all practical uses of the 74HC595 IC. For instance, the SRCLR signal is not used and is permanently tied to VCC so that it never clears the register; this of course, may not suit your needs, however the code is heavily commented and adaptation of the code should be fairly simple.

The functional operation of the module can be seen in this timing diagram simulation:

The yellow markers are showing the beginning and end of one complete 8-bit shift operation. This simulation is using a 50ns clock period which is slightly slower than the 24MHz clock that my actual FPGA is using. This simulation shows that it takes about 89 clocks to process a request. 89 clocks at 24MHz is about 3.7us.

Signal Descriptions:

  • RDY: A bit that indicates that the FPGA_2_ShiftReg is idle and is ready to process a request
  • RCLK: A signal sent to the shift register which instructs the output registers to read from the shift register taps
  • SRCLK: A signal sent to the shift register which instructs the 8-bit shift register to shift the register bits and read from the serial input and push it into the LSB.
  • OE: A signal sent to the shift register which sets the output in either Hi-Z (output disabled) or Lo-Z (output enabled). This is an active low signal.
  • SER_OUT: The Serial signal sent to the shift register.
  • CLK: The FPGA's local oscillator which drives the rest of the logic.
  • BYTE_IN: An 8-bit value that is fed into the FPGA_2_ShiftReg module
  • PB: A signal created for simulation purposes to instruct the module to read the 8-bit value from BYTE_IN. Every time this pushbutton is pressed the FPGA_2_ShiftReg module is activated and instructed to read the BYTE_IN. Also the driving module (the module that instantiates and uses the FPGA_2_ShiftReg module) increments the BYTE_IN value by one.


  1. I've worked on a YL-3 driver for Verilog, but had some issues ( I thought I would re-do it, and found your code. Since yours only send 8 bits at a time, I tried to make it 16, which some what worked. I could get the position right, but not the character to display right (I think there needs to be a delay between two 8 bit shifts). My Verilog skills are pretty crappy and thought I would reach out to you to see if you could help me out on this.

    1. Hi Ellis,
      I will give it some thought. If I understand correctly, you want to effectively push in 16 bits and then strobe RCLK so that the outputs are updated only after all 16-bits have been shifted into place. Correct?

      I decided to create an actual github repo for this code. You can access it in the link below. I did some small cleanup and formatting that may help with readability:

      If this code can be adapted to make it flexible to have any number of shift registers daisy-chained together this would be a great addition to the code.