tag:blogger.com,1999:blog-3692466414896854875.post9042568621549744726..comments2023-05-06T06:54:24.300-04:00Comments on The Carrier Frequency: FPGA to 74HC595 Shift Register Module in VerilogAnonymoushttp://www.blogger.com/profile/15340615281188281462noreply@blogger.comBlogger2125tag:blogger.com,1999:blog-3692466414896854875.post-82489294550077089622017-04-16T14:31:46.315-04:002017-04-16T14:31:46.315-04:00Hi Ellis,
I will give it some thought. If I unders...Hi Ellis,<br />I will give it some thought. If I understand correctly, you want to effectively push in 16 bits and then strobe RCLK so that the outputs are updated only after all 16-bits have been shifted into place. Correct?<br /><br />I decided to create an actual github repo for this code. You can access it in the link below. I did some small cleanup and formatting that may help with readability:<br /><br />https://github.com/jjcarrier/FPGA_2_ShiftReg<br /><br />If this code can be adapted to make it flexible to have any number of shift registers daisy-chained together this would be a great addition to the code.Anonymoushttps://www.blogger.com/profile/15340615281188281462noreply@blogger.comtag:blogger.com,1999:blog-3692466414896854875.post-8532543589020474472017-04-13T00:44:54.740-04:002017-04-13T00:44:54.740-04:00I've worked on a YL-3 driver for Verilog, but ...I've worked on a YL-3 driver for Verilog, but had some issues (https://www.youtube.com/watch?v=TBHh_up2X0k). I thought I would re-do it, and found your code. Since yours only send 8 bits at a time, I tried to make it 16, which some what worked. I could get the position right, but not the character to display right (I think there needs to be a delay between two 8 bit shifts). My Verilog skills are pretty crappy and thought I would reach out to you to see if you could help me out on this.Ellishttps://www.blogger.com/profile/17827868390661626279noreply@blogger.com