Wednesday, January 22, 2014

Plain Simple Hardware Description Language (PSHDL)

I stumbled across an interesting post that led me to this site:
pshdl.org

It seems that there is an effort to create a new language that replaces/overlays traditional HDL such as Verilog and VHDL. The thought is that these languages originate pre-FPGA and have a lot of non-synthesizable concepts built into them. PSHDL may become a language that simplifies the general learning curve and process of realizing synthesizable designs. If you go to the root page of the link sited above, it will bring you to a webtool for generating equivalent, presumably, synthesizable HDL code.

Sunday, November 24, 2013

PWM VHDL Module

Here is yet another PWM (Pulse Width Modulation) module! What distinguishes this module from most other PWM modules is that it's parameterized. When dealing with LEDs this becomes a very useful feature since each type of LED responds differently (in terms of light) when presented with a PWM signal. This module will allow you to adjust the clock prescaler and the number of quantas. What does this mean you ask? Let me explain with the help of a simple picture...


Basically the PWM signal is produced via a multi-process module. The first process is a "prescaling process". This process takes the input clock and divides it down by the amount you specify. This process is not critical towards its operation and could be removed if you want to minimize your logic.

The next process is the "Accumulate process". This process is responsible for determining when to switch the PWM outputs logic state. Basically it takes the prescaler's divided clock and accumulates/increments a counter on each cycle. One time "quanta" is equivalent to one cycle of the PWM divided clock.

The final process is the "modulate" process. This is the key process to generating the PWM signal. It determines when to switch the PWM output signal based on the PWM accumulator and the PWM input signal. The accumulator continually counts up towards the maximum quanta value and then rolls over to 0 where the process continues to count. The PWM input determines when to bring the PWM output low. A larger PWM input means the PWM output will remain HI for a longer period of time which produces a brighter output on the LED (or dimmer depending on how the LED is connected). In order to maintain a constant level of illumination it is important to ensure that the refresh rate of the PWM cycle is above the human eye's flicker fusion rate. This is generally understood to be around 16Hz but you should target 60Hz or higher. The general criteria for these configurable parameters should satisfy the following equation:

60<=(f_CLK/prescaler)/quantas

For instance, a 100MHz clock prescaled by 3125 with 128 time quantas yields a refresh rate of 250Hz which is well above the minimum and should be visually flicker-free.

Here is a demo of this module running on a Terasic DE0-NANO.

video


Download: PWM.vhd

Friday, November 22, 2013

Gtk+ Si47xx Radio

Well...it's been a while since I have posted anything. So here is a little teaser of something that I have been casually working on. This is another radio project, this time on a RaspberryPi (RPi) using the same Si4735 chip as my other radio project and using a revamped object oriented design on the Si47xx library. Currently, this Gtk+ GUI you see below runs directly off of the RPi and I use X11 Forwarding to bring the GUI to my local PC, effectively giving me remote control over the radio. But as you can see from the GUI's "Network" menu item. I am in the process of bringing this GUI to the local PC and then remotely connect to a radio server that runs on the RPi. This will be (most likely) a TCP socket where the server will push the RDS/RBDS data to the client and the client will populate the corresponding GUI elements with the received data.

video


Unfortunately, I am not ready to share the sources publicly, but fear not, this will be made public in the future.