I stumbled across an interesting post that led me to this site:
pshdl.org
It seems that there is an effort to create a new language that replaces/overlays traditional HDL such as Verilog and VHDL. The thought is that these languages originate pre-FPGA and have a lot of non-synthesizable concepts built into them. PSHDL may become a language that simplifies the general learning curve and process of realizing synthesizable designs. If you go to the root page of the link sited above, it will bring you to a webtool for generating equivalent, presumably, synthesizable HDL code.
